risc

risc

1. Samsung S3C2440A SOC RISC Microprocessor test program that demonstrates how to code most peripherals on the chip.

(译)：三星S3C2440A RISC微处理器的SOC测试程序，演示了如何代码最外围芯片上。

2. The Function and Application of the 16-bit RISC Core Microcontroller

16位RISC内核微控制器MAXQ3210的功能和应用

3. Apple and IBM signed a pact to form a jointly owned software company that would create a new operating system designed for the RISC (Reduced Instruction Set Computer) processor .

1991年7月3日，苹果公司和IBM公司两大软件公司，签定了建立新的联合软件公司的合同。联合公司将为RISC（精简指令集计算机）处理器开发一个新的操作系统。

4. Design of Internal Clock Circuit for A 32-b RISC Microprocessor

32位RISC微处理器内部时钟电路的设计

5. Research on 32-bit RISC Microprocessor Design

32位RISC微处理器设计研究

6. DESIGN OF A 32-BIT EMBEDDED RISC MICROPROCESSOR

32位嵌入式RISC微处理器的设计

7. Design and Realization of A 32-bit Embedded RISC Microprocessor

32位嵌入式RISC微处理器设计与实现

8. 32 Bit Embedded RISC Microcomputer

32位嵌入式RISC微计算机

9. A Design of 8-bit RISC MCU IP Core

8位RISC MCU IP核的设计

10. The AMBA bus consists of AHB/ASB(Advanced High-performance Bus) and APB(Advance Peripheral Bus). RISC processor,IP and peripheral apparatus are integrated by AMBA bus.

AMBA总线由高速总线AHB/ASB(Advanced H igh-performance Bus)和低速总线APB(Advance Peripher-al Bus)2种总线机制组成,实现R ISC处理器、IP核和外设集成。

11. Advanced RISC (reduced instruction set computer) Machines (ARM)

ARM

12. ARM ( advanced RISC machines) microprocessor

ARM微处理器

13. ARM processor is an advanced 32 bit RISC(Reduced Instruction Set Computer) mpu with low power, high performance and small size, which is suitable for the condition of portable instrument, embedded type and multimedia.

ARM微处理器是一款高性能、低功耗、体积小的32位RISC(精简指令集计算机)处理器,适合于便携式、嵌入式和多媒体应用领域。

14. Most of the design features of the CDC 6600 and the CRAY-1 computers recall the foundation of the RISC design philosophy.

CDC 6600和CRAY-1的大部分设计特点使人回想起RISC设计思想的基础。

15. CISC and RISC are the two main instruction systems for MCU design.

CISC与R ISC是目前微控制器(MCU)设计的两种主要指令体系。

16. They could be partitioned two sorts by Structured Computer Organization. One is Complex Instruction Set Computer (CISC), another is Reduced Instruction Set Computer (RISC).

CPU的分类方法很多，最为典型的是按照体系结构把它们分为复杂指令集处理器(CISC)和精简指令集处理器(RISC)。

17. The emphasis in CPU design shifted to raw performance, and RISC became the new philosophy.

cpu设计的重点转到了提高性能上，risc成了新的（设计）思想。

18. The company such as IBMSun and SGI sold 90 him % of RISC (computer of compact instruction collect) the workstation of processor.But.

HP．IBMSun和SGI等公司销售了90%自己的装有RISC（精简指令集计算机）处理器的工作站。

19. A STRATEGY FOR WHOLE MACHINE BEHAVIORAL FUNCTIONAL LEVEL SIMULATION OF MB86901 SPARC RISC CHIP

MB86901 SPARC RISC芯片全机行为功能级模拟策略的研究

20. MPC555 is a 32-bit microcontroller, with RISC CPU in it and PowerPC compatible instruction set architecture.

MPC555是一款PowerPC体系结构、采用RISC CPU技术的32位微控制器。

21. OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar32- bit RISC processors in his class and can efficiently run any modern operating system.

OR1200定位于嵌入式、动和网络应用。她能够与同类的最新的32位标量处理器竞争，并且可以运行任何现代操作系统。

22. The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.

OR1200是一种32位、标量、哈佛微体系结构、5级整数流水线RISC，支持虚拟存储器和基本的DSP功能。

23. PHP can be used on all major operating systems, including Linux, many Unix variants (including HP-UX, Solaris and OpenBSD), Microsoft Windows, Mac OS X, RISC OS, and probably others.

PHP能够用在所有的主流操作系统上,包括Linux、Unix的各种变种(包括HP-UX、Solaris和OpenBSD)、Microsoft Windows、Mac OS X、RISC OS等。

24. POWER stands for Power Optimization With Enhanced RISC and is the main processor in many IBM servers, workstations, and supercomputers.

POWER是Power Optimization With Enhanced RISC的缩写,是IBM的很多服务器、工作站和超级计算机的主要处理器。

25. RISC is the abbreviation of Reduced Instruction Set Computer. It has features of simple instruction, low power consumption and fast operation speed.

RISC(Reduced Instruction Set Computer)是精简指令集计算机,它具有指令简单、功耗低、运行速度快的特点。

26. Finally.what is the major difference between a RISC microprocessor and a CISC one?

RISC与CISC最后要讨论的是，RISC微处理器和CISC微处理器之间的只要区别何在？

27. The Architecture Compare of RISC With DSPand the Choice Scheme in Embedded Application

RISC与DSP的结构比较及在嵌入式应用中的方案选择

28. The project focuses on a RISC-CPU and develops an IC design flow. RISC is the acronym of Reduced Instruction Set Computer.

RISC即精简指令集计算机(Reduced Instruction Set Computer)的缩写。

29. Comparison between RISC and CISC Micro-controller

RISC和CISC两种构架MCU的比较

30. RISC processors generally feature fixed-length instructions, a load-store memory architecture, and a large number of general-purpose registers and/ or register windows.

risc处理器一般的特征是固定长度的指令集，一个负载储备存储结构，和大量通用寄存器，及寄存器窗口。

31. RISC processors, because they are software-programmable, provide the flexibility to get adapted to the rapidly evolving data communications market.

risc处理器由于是可编程的，故提供了灵活性，以适应快速发展的数据通信市常

32. RISC processors are used in many small devices such as PDA, mobile phones, clever coffee-machines etc.There is a big variety of assemblers for RISC processors, but the most frequent one now is ARM.

RISC处理器的使用在许多小型设备，如掌上电脑，移动电话，聪明的咖啡机等,有很大的不同的装配的RISC处理器，但最常见的一个是ARM。

33. CACHE DESIGN OF RISC WORKSTATIONS

RISC工作站的Cache设计

34. The SMP multi-processors system building by RISC microprocessors is one of the methods of high-performance computer.

RISC微处理器构造的对称多处理SMP多机系统是高性能计算机的一个发展方向。

35. RISC TECHNOLOGY OPEN SYSTEM AND THEIR INFLUENCES ON SCADA/EMS

RISC技术与开放式系统及其对SCADA/EMS系统的影响

36. RISC technique in star sensor

RISC技术在星敏感器中的应用

37. The major tenet of RISC states that much of the static runtime complexity can and should be handle prior to runtime by an optimizing compiler.

RISC的主要原则表明许多固定运行时间的复杂指令可以并且应该由优化编译器先于运行时间进行处理。

38. The simplicity of RISC also makes it easier to design superscalar processors -- chips that can execute more than one instruction at a time.This is called instruction-level parallelism.

RISC的简单性也使设计超级标量处理器较为容易，这种芯片一次能执行几个指令，这被称为指令级的并行处理。

39. Seymour Cray has achieved recognition as a pioneer of RISC architectures.

RISC的设计可以追溯到第一台电子计算机。

40. RISC chips use a rather small number of relatively simple, fixed-length instructions, always 32 bits long.

risc芯片采用数量较少、较为简单的固定长度指令，总是32位长。

41. RISC Design and Hardware Architecture

RISC设计和硬件结构

42. In order to design the resulting architecture,the designer must keep in mind a coherent set of characteristics that are typical of RISC implementations.

RISC设计规范下面是纯粹RISC结构的典型特性并得到大多数设计师的赞同。

43. Realization of BootLoader on S3C44B0X RISC Microprocessor

S3C44B0X中BootLoader的实现

44. The Samsung S3C44BOX CPU is 32/16 bit RISC Microprocessor and uses ARM7TDMI core. Its maximum CPU clock frequency is 75Mhz. The S3C44BOX is used in fields of cheap price handle devices and industry applications.

Samsung S3C44BOX是32/16位RISC微处理器，它使用ARM7TDMI内核，最高频率可达75MHZ，主要用于廉价手持设备和一般工业应用领域。

45. SDU_M08 is an 8-bit RISC Microcontroller Unit IP core. It is compatible with the instruction set of PIC16C57 of Microchip Corporation.

SDU_M08是一种与Microchip公司的PIC16C57指令集完全兼容的8位RISCMCU IP核，本文研究了功能验证在SDU_M08验证中的应用。

46. The Nios embedded processor is a softcore 16/32 bits RISC CPU optimized for Altera programmable logic devices.

SoPC(Svsetm on Programmable Chip)是基于可编程逻辑的片上系统,Nios处理器是一个基于FPGA的16/32位的软核RISC处理器。

47. It uses RISC to calculate the LPC coefficients used to design the TNS decoding filter,and also optimizes the code. TNS decoding filter is described by Verilog HDL,and validates the whole Soc system on FPGA.

TNS解码模块中所需要的滤波系数通过RISC指令计算并对算法进行了优化,滤波解码部分用硬件Verilog语言描述并在整个Soc系统中通过FPGA验证。

48. VLIW has become the prevailing philosophy of microprocessor design, eclipsing older approaches such as RISC and complex instruction set computing (CISC).

VLIW已经成为一种具有优势的微处理器设计方法，开始侵蚀RISC（精简指令集计算）和CISC（复杂指令集计算）较陈旧的设计方法。

49. A poor VLIW compiler will have a much greater negative impact on performance than would a poor RISC or CISC compiler.

一个差的VLIW编译器对（系统）性能的负面影响超过差的RISC或CISC编译器的影响。

50. The Research of 8 BIT RISC MCU Core

一种8 BIT RISC MCU内核的研究

51. Synthesis of an 8 b RISC MCU

一种8bRISC微处理器的综合

52. Design of ALU Based on an 8_Bit RISC Singlechip

一种8位单片机中ALU的改进设计

53. Design and Realization of an Address Generator Algorithm for RISC

一种RISC地址产生器生成算法的设计与实例化

54. Design and Implementation of Fast Computation for Multiplication and Division Embedded in RISC Processor

一种RISC微处理器的快速乘除法运算设计与实现

55. A Method for Speeding-up Instruction Reading in EEPROM of the Embedded RISC Microprocessor

一种加速嵌入式RISC微处理器EEPROM指令读取的方法

56. The Architecture of An Embedded 32 Bit RISC Microprocessor

一种嵌入式32位RISC微型计算机的体系结构

57. Design of an Integer Execution Unit in an Embedded RISC Microprocessor

一种嵌入式RISC微处理器的整数部件设计

58. Global Scheduling Technique of Delay Slot on RISC Architecture

一种面向RISC体系结构的全局延迟槽调度策略

59. A RISC Style Collaborative Framework for Mission Critical System

一种面向任务关键系统的RISC风格的协作构架

60. Design of RISC Microcontroller with High Code Density

一种高代码密度RISC结构微控器的设计

61. The following characteristics are typical of pure RISC architecture and most designers agreen on them.

下面是纯粹RISC结构的典型特性并得到大多数设计师的赞同。

62. VLIW chips can cost less, burn less power and achieve significantly higher performance than comparable RISC and CISC chips.

与RISC和CISC芯片相比，VLIW芯片的成本低、功耗低、并能获得更高的性能。

63. Rather,RISC tries mainly to reduce the average number of clock cycles per instruction(CPI).

两种结构均想通过使用高速技术来提高时钟频率。

64. ARM - The Architecture for the Digital World - [ ]ARM is a leader in microprocessor Intellectual Property. ARM designs and licenses fast, low-cost, power-efficient RISC processors, peripherals and ...

中文--[]公司设计先进的数字产品核心应用技术，应用领域涉及：无线、网络、消费娱乐、影像、汽车电子、安全应用及存储装置。

65. To prevent 1 death, the number needed to scan was 17 based on TRISS and 32 based on RISC calculation.

为了预防1件死亡，根据TRISS，需要扫描17人，根据RISC，需要扫描32人。

66. For purpose of illustration, a RISC processor that embeds a direct-mapped data cache is employed for the experiments.

为了验证我们的测试方法，我们使用一个拥有直接映射记忆体的处理器来当我们的测试样本。

67. Design and implementation of 8-bit MCU I P Core based in system structure of RISC are presented.

介绍了一种基于RISC体系结构的微控制器IP核---8位MCU Core的设计与实现。

68. A design of software and hardware on building automatic remote intelligent manager is introduced and a hardware platform made up of FS44B0XI chip,which is based on ARM7TDMI core 32 digits RISC fabric is adopted.

介绍了一种楼宇自动化远程智能化管理器的软、硬件设计,它采用基于ARM7TDMI内核的32位RISC结构的FS44B0XI芯片构成硬件平台。

69. The paper introduces a method to develop a high precise DDS signal source based on CPU soft nucleus Nios of RISC in Altera Company.

介绍了以Altera公司的RISC结构的CPU软核Nios为基础,利用Quartus软件和SoPCBuilder设计的一种精度较高的DDS信号源。

70. Since the invention of the first ARM prototype in Cambridge in England,the 32-bit ARM RISC CPU has been used in all kinds of fields and it has occupied most marcket of the 32-bit application.

从1985年第一个ARM原型在英国剑桥诞生以来,ARM32位嵌入式RISC处理器的应用已经扩展到各个领域,占据了32位应用的大部分市场。

71. In keeping with their glorious tradition, they will certainly risc against the aggressors.

他们一定会按照他们的光荣传统，起来反击侵略者。

72. His work on RISC and optimizing compilers won him many awards, not the least of which was the 1987 Turing Award.

他在RISC和编译器优化方面的工作为他赢得了很多荣誉,其中包括1987年的图灵奖。

73. Taking the CPU core of the 8-byte RISC system as example to show how to combine thetwo technics of IC design by IP core and FPGA are given, and a method of the modules'Verificationand testing of IP core are shown.

以一个8位的RISC体系的CPU核为例,介绍了如何将IC设计中的IPCore和FPGA两项技术结合起来,并给出了IP核模块的验证与测试的方法。

74. Traditional Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) have different application areas due to their different Instruction Set Architecture (ISA) and micro-architecture.

传统的精简指令集处理器(RISC)和数字信号处理器(DSP)各自具有不同的指令集结构和微结构特点，适合于不同的应用领域。

75. While complex instructions have many pitfalls, a small number of carefully selected complex instructions can usefully increase the performance of both CISC and RISC processors.

但经过周密考虑所选择的少量复杂指令有助于提高CISC和RISC微处理器的性能.

76. Keywords Low-Power design,Flip-Flop,Sequential Circuit,RISC,Superscalar;

低功耗设计;触发器;时序电路;精简指令计算结构;超标量微处理器;

77. Low Power Logic Circuits Design and Application in Risc Design

低功耗逻辑电路设计及在RISC设计中的研究

78. "It provides a high level design for a thorough optimizer, code generator, scheduler and register allocator for a generic modern RISC processor.

作者在编译器的实践方面经验丰富，主要关注如何选择编译技术，技术的工程实现以及如何对技术进行改进。

79. Keywords HDTV,Integrated Source Decoder Chip,HW/SW Co Design,RISC,VM,RTOS;

信源集成解码芯片;软硬件协同设计;RISC;虚拟机;实时操作系统;

80. ARM ( advanced RISC machines )

先进精简指令微处理器