sdram
sdram
1. ddr sdram
(double date rate双数据率sdram)
2. sdr sdram
(single date rate单数据率sdram)
3. DDR SDRAM design and debugging experience.
(译)：DDR SDRAM内存的设计和调试经验。
4. ddr sdram controller datd module source code integrity of the source code has been tested.
(译)：DDR SDRAM控制器模块的源代码datd完整的源代码已经过测试。
5. DSP TS201 Test SDRAM Over the full source code can be used directly.
(译)：基于DSP TS201测试内存在的全部源代码可以直接使用。
6. It sa SDRAM Controller reference design.
(译)：它山SDRAM控制器参考设计。
7. For the problem of huge data storage, use SDRAM to store the data, and use FPGA to control SDRAM to complete the transpose.
2.为了解决数据量庞大、高速数据存取的问题,本文采用了FPGA芯片和同步动态存储器(SDRAM)来实现矩阵转置运算。
8. The design of CPLD has adopted the output clock of image sensor to write SDRAM.
CPLD电路设计采用图像传感器的输出时钟触发SDRAM写过程.
9. DDR FCRAM Boosts Performance in DDR SDRAM Designs
DDR FCRAM改进DDR SDRAM设计性能
10. The Design and Implementation of DDR SDRAM Controller
DDR SDRAM控制器的设计与实现
11. DDR SDRAM is a high speed and largecapacity memory,but because of the need of synchronous clock and the characteristic that it is controlled by control command,there must be a controller between the system and DDR SDRAM.
DDR SDRAM是一种大容量,高速度的同步动态存储器,但是由于其对同步性的要求以及需要由控制字来控制的特点使得他与系统之间必须有一个接口来实现时钟同步和对DDR SDRAM进行控制。
12. Implementation of DDR2 SDRAM Controller in a FPGA
DDR2 SDRAM控制器的FPGA实现
13. DDR2 SDRAM
DDR2SDRAM
14. DDR2 SDRAM module controller
DDR2内存条控制器
15. DDR SDRAM(Doultle Data Rate SDRAM)
DDR内存储器
16. Since DDR memory in the clock rising edge and falling edge of the transmission of data can, therefore, at the same clock frequency and data-bit width memory bandwidth cases are twice as common SDRAM.
DDR显存因为能在时钟的上升沿和下降沿都能传送数据，因此，在相同的时钟频率和数据位宽度的情况下显存带宽是普通SDRAM的两倍。
17. RAM comes in many varieties, including dynamic RAM (DRAM), synchronous RAM and synchronous dynamic RAM (SDRAM).
RAM有多种形式，包括动态RAM（DRAM）、同步RAM和同步动态RAM（SDRAM）。
18. Registered SDRAM
Registered内存
19. synchronized dynamic random access memory(SDRAM)
SDRAM
20. SDRAM is connected to the 64bit data bus of EMIF, can read/write 64bit data at every cpu cycle, be used to store program, data and image.
SDRAM与外部存储器接口的64位数据线相连，每次可读/写64位数据，用来存储程序、数据和视频信息。
21. SDRAM can be synchronized with the CPU work, without waiting for the cycle to reduce the data transmission delay.
SDRAM可以与CPU同步工作，无等待周期，减少数据传输延迟。
22. Application of SDRAM in Ethernet port of EOS
SDRAM在EOS中以太网口的应用
23. SDRAM controller
SDRAM控制器
24. The functions of SDRAM control module and VGA display module are as follows.SDRAM control module can temporarily store images captured by the CCD camera.
SDRAM控制模组与VGA显示模组各有不同功能：SDRAM控制模组可暂存CCD所撷取到的影像；
25. SDRAM is one kind of high density memory device.
SDRAM是一种高密度的存储器件，可以通过电性测试，并且运用bitmap这一有效工具诊断出其具体的失效区域，通过进一步的物性失效分析来找出工艺上失效的原因。
26. Supported memory SGRAM block write and mask, can be seen as the enhanced version of SDRAM, the popular, but because of the price slightly higher than SDRAM, and now has been little used.
SGRAM显存支持块写和掩码，可以看作是SDRAM的加强版，曾流行一时，但由于价格较SDRAM稍高，现在也已甚少采用。
27. Implementation of DDR SDRAM Controller Based on FPGA
一种DDR SDRAM控制器设计
28. Design of Virtual DDR SDRAM Used for High Speed Communications and Its Implementation with FPGA
一种用于高速通信的虚拟DDR存储器设计及其FPGA实现
29. Main Products : FLASH、SDRAM、SRAM、EEPROM、MCU、POWER IC、LOGIC IC.Source of worldwide components in shortage.
主营：FLASH、SDRAM、SRAM、EEPROM、MCU、POWER IC、LOGIC IC、光耦、及全球紧缺料搜寻等。
30. principle and implementing method of SDRAM are introduced simply in this paper.
介绍了SDRAM的工作原理和使用方法。
31. The shared devices (SDRAM and AD) are fast arbitrated in hardware and the shared devices' access conflicts are resolved, so the continuous data acquisition is realized.
从硬件上实现了共享器件(SDRAM和AD转换器)的高速仲裁，避免了共享器件的访问冲突，从而实现了连续采集。
32. While its time sequence and access mechanisms are very complex, it is necessary to design SDRAM controller to improve the efficiency of accessing.
但SDRAM的控制时序和机制较复杂，因此需要设计SDRAM控制器以提高其读写效率。
33. Compared with the DDR SDRAM, DDR2 SDRAM has higher speed, lower power, higher efficiency and higher stability.
作为第2代DDR存储器的DDR2SDRAM具有高速、低功耗、高密度、高稳定性等特点,在未来的一二年里,它将逐步取代DDRSDRAM而成为内存的主流。
34. The platform uses a floating point DSP (Digital Signal Processor) TMS320C6713, and a SDRAM (Synchronous Dynamic Random Access Memory).
其中,使用了浮点型数字信号处理器(DSP)TMS320C6713、同步动态RAM(SDRAM)。
35. Increased memory: 8 MB SDRAM provide not only enough space for the most complex configurations of large multi-node installations, it includes even plenty of headroom for future developments.
内存增加:8MB SDRAM不仅提供了足够的空间用于最复杂的大型多节点配置,还为将来的功能升级提供了足够的储备空间。
36. DDR is the acronym for Double Data Rate Synchronous DRAM (SDRAM).
加，因此它的传输效能比同步动态随机存取内存(SDRAM)好。
37. the memory module which includes a 32M bytes Flash memory and a 32M bytes SDRAM;
包括32M字节容量Flash和32M字节容量SDRAM的存储模块；
38. DDR SDRAM (Double Date Rate Synchronous Dynamic Random Access Memory)
双通道同步动态随机存储器(双信道同步动态随机存取内存)即
39. Another MS6301 uses the design of 3 DIMM chamfer only, so that be in,at present RAMBUS memory price uses SDRAM memory below higher case.
另一款 MS6301则只采用3根 DIMM 槽的设计,以便在目前 RAMBUS内存价格较高的情形下使用 SDRAM 内存。
40. Compared with traditional controller through experiments the novel SDRAM controller gets a high reduction up to 63% in access waiting time and 64% in page miss.
同时还使用了四路组关联的片上堆栈存储器来降低SDRAM的页失效频率，从而降低了因页失效而需要等待的时钟周期。
41. Similarly, DDR memory bandwidth to achieve a common 2-fold of SDRAM memory.
同样，DDR显存达到的带宽也是普通SDRAM显存的2倍。
42. Synchronous Dynamic Random Access Memory (SDRAM)
同步动态随机存储器
43. The SDRAM has become the chief choice of the buffer storage because of its high speed, great capacity, and low price;but due to its complex control timing, it cannot directly interface with DSP.
同步动态随机存储器(SDRAM)具有高速,大容量,价格低廉等优点,因而成为缓冲存储器的首选,但是SDRAM控制时序比较复杂,不能与DSP直接接口,这极大地限制了它的广泛应用。
44. DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory.
同步双数据传输率动态随机存储器,通常简称DDR。
45. Glueless Interface to Synchronous Memories: SDRAM
同步存储器接口
46. QDR SDRAM Quad Data Rate
四倍速率 SDRAM
47. In the GA module, FPGA is used to carry out the function, large volume DDR SDRAM is used to capture and store data, and Real Time Operating System(RTOS) is adopted to configure and manage test system.
在分析模块中，使用大规模可编 程逻辑芯片FPGA 来完成主要的测试功能，使用大容量存储器进行数据的捕捉存储。以及 使用实时操作系统进行系统管理配置等。
48. This design uses a SDRAM as off-chip memory to reduce the sum of chip's I/O.
在帧存储设计中，本文采用一块SDRAM作为片外帧存储器减少芯片I/O引脚、降低了成本。
49. Based on the analysis of the SDRAM and DDR memory architecture,this paper presents the design principals of MBM and offers the implementation and the actual waveforms.
在详细分析了SDRAM和DDR存储器结构的基础上,提出了MBM的设计思想,并给出了其实现方法和实际波形。
50. Study and Implementation of DDR2 SDRAM Controller Based on AMBA Bus
基于AMBA总线的DDR2 SDRAM控制器研究与实现
51. Timing Logical Expression Based on DDR SDRAM Controller Signals
基于DDR SDRAM控制器时序分析的模型
52. A Implementation of DDR SDRAM Controller based on FPGA
基于FPGA的DDR SDRAM控制器的实现
53. FPGA-based DDR SDRAM Controller Implementation
基于FPGA的DDR SDRAM控制器设计与实现
54. Large capacity SDRAM
大容量SDRAM
55. A computer can access data in SRAM more quickly than it can access data in DRAM or SDRAM.
大概上七八周十四天的课，一个班里面一名外教和四至八名的学生。
56. It uses a 90 nanometer traces, and includes 128KB L1 cache + 256KB L2 cache and its own memory controller for DDR SDRAM, with a "hyper-transport link" of up to 800 MHz.
它采用90纳米的痕迹，其中包括128KB的一级缓存+ 256KB的L2高速缓存和自己的内存控制器为DDR SDRAM内存，以“超运输联系”的高达800兆赫。
57. As for the hardwire on the target board, we mainly recommend the power source, JTAG, Flash, SDRAM, Ethernet and serial port.
对于目标板的硬件主要介绍了电源、JTAG接口、Flash和SDRAM存储器、以太网、串行口等模块。
58. It focuses on the design of hardware framework about DSP-based embedded face recognition door manager system including the detailed technology of circuit design amoung image sensor, DSP, Flash, SDRAM, RS232 serial port, timer and resetting.
对基于DSP的嵌入式人像识别门禁系统的硬件架构的设计进行了探讨,包含了图像传感器、DSP芯片、Flash、SDRAM、RS232串口、时钟、复位电路等硬件的具体实现技术。
59. Local data storage is an important part of digital imaging system, and SDRAM is in common use.But the system need special control module because the accessing timing of SDRAM is complex.
局部数据存储是成像系统不可或缺的一部分，一般采用SDRAM作为存储介质，由于SDRAM的访问时序比较复杂，因此需要专用的控制模块。
60. Meanwhile, to reduce the waiting time aroused by page miss of SDRAM, a four ways of on chip stack memory is introduced.
并引入了两组双通道预取指令缓冲器，每组双通道都用以减少取指令时的等待时间，采用两组的结构是为了增加指令预取的命中率；
61. DDR SDRAM leads memory industry to a new step
引领内存新风采
62. Sensor control module, SDRAM control module and VGA display module compose a system which can capture and display images at the same time without being controlled by the core processors.
影像撷取模组、SDRAM控制模组与VGA显示模组，三者可组成即时的影像显示与撷取系统，在不经过核心处理器的控制下，可达到即时的影像显示与撷取。
63. Looking SDRAM / DDR RAM module offer, new or refurbish also welcome. Quote your best offer. Thanks.
您现在还未登陆，请登陆后查看该采购客商的联系方式。
64. We want to buy DVD, VCD, VCR, Memory Ddr, Sdram and DVD Media 4X, 8X
我们要采购消费电子产品，电池，数字化视频光，可变电容二极体,录象机，DVD,VCD,VCR
65. In other words, the memory speed at the same circumstances, DDR memory are the actual operating frequency of 2 ordinary SDRAM memory times.
换句话说，在显存速度相同的情况下，DDR显存的实际工作频率是普通SDRAM显存的2倍。
66. Power Integrity Research of DDR SDRAM Control Circuit
控制电路电源完整性研究
67. As mass storage body, SDRAM has extensive usable value in high data processing.
摘要SDRAM作为大容量存储器在高速数据处理系统中具有很大的应用价值。
68. A high performance SDRAM controller orienting to system on chip is designed by analyzing the access of SDRAM.
摘要在分析了SDRAM存取原理之后，提出并设计了一种面向片上系统的高性能SDRAM控制器。
69. The speed of SDRAM, therefore, is not measured in the familiar old nanoseconds but in megahertz, like processors.
故而，sdram的速度不再用大家熟悉的纳秒来度量，而像处理器那样用兆赫（mhz）来度量。
70. A method of "Hierarchy" is put forward, a SDRAM MODULES controller is designed based on CPLD, and the application of SDRAM MODULES in engineering is also solved in the paper.
文中提出了层次式的设计方法，并用该方法设计了一种基于CPLD的SDRAM内存条控制器，从而解决了内存条的工程应用问题。
71. The type of memory has EDORAM, MDRAM, SDRAM, SGRAM, VRAM, WRAM, DDR, and many other species.
显存的种类有EDORAM、MDRAM、SDRAM、SGRAM、VRAM、WRAM、DDR等许多种。
72. Abstract: The article introduce a method based on FPGA technology implements the data transmission between the PC COM Port and a external SDRAM.
本文主要介绍了一种基于FPGA技术实现PC串口与外部SDRAM之间数据传输的方法。
73. Based on the design of instruction pre-fetch FIFO for an embedded RISC processor, a SDRAM power model has been presented to optimizing the FIFO design.
本文从一个嵌入式RISC处理器的指令FIFO设计出发，提出了SDRAM的功耗模型，基于该功耗模型，提出了最优化的指令FIFO设计。
74. The SDRAM controller function module designed in this paper accesses the SDRAM with medium-high speed and accomplishes the general function.
本文所设计的SDRAM控制器功能模块具备中高速的访问能力，完成SDRAM的通用功能。
75. The article introduces the basic character of DDR2 SDRAM based on DDR2 speciation. It compares the differences between DDR and DDR2 speciation and analyzes the future of it.
本文根据已有的内存技术标准,主要介绍了DDR2 SDRAM的基本特征,比较其与DDR技术规范的不同,最后分析了DDR2技术的未来发展。
76. This paper realizes a general SDRAM controller function module on FPGA device, which satisfying the requirements of medical imaging system.
本文还根据医学成像系统的要求，以FPGA器件为平台，实现了通用的SDRAM控制器功能模块。
77. Through the research of two important problems in SAR real-time processing, succeed in realizing of the block floating FFT based on FPGA, and complete the transpose using FPGA and SDRAM.
本课题以SAR实时成像处理系统的研制为背景,通过对SAR实时成像处理系统两个主要问题的研究,成功完成了利用FPGA实现块浮点FFT运算,并对SDRAM的控制完成矩阵转置板的转置功能。
78. This application creates an USB Mass Storage drive on a host computer. The drive is created from thee internal Flash or external SDRAM memory of the evaluation kit.
本资源为高质量源码,需要会员才能下载,如果你是会员，请登陆。如果不是会员请注册。
79. According to the timing characteristics of SDRAM, the design makes use of a VHDL state machine,with focus on the implementation of techniques of multi-port memory controller.
根据SDRAM器件的控制时序特点,采用VHDL状态机的设计方法实现了多端口存储控制器的技术。
80. Slow memory (FPM / EDO / BEDO) detected. Upgrade to SDRAM or RDRAM if possible.
检测到低速内存(FPM/EDO/BEDO). 可能的话请升级到 SDRAM 或 RDRAM.
